Since their inception, normally off enhancement mode (e-mode) gallium nitride (GaN) transistors have demonstrated superior in-circuit performance compared to conventional silicon technologies. E-mode GaN transistors, and wide bandgap power devices in general, are capable of higher performance than silicon MOSFET technology and have led to the development of improved applications fundamentals to fully utilize the capability of the superior power devices and better optimize designs around the unique device properties.
For e-mode GaN transistors, one distinct device property is a lower maximum gate voltage capability when compared to standard silicon MOSFETs. Specifically, the gate overhead margin, which is defined as the difference between the manufacturers recommended gate voltage and the maximum gate voltage of the device, is small for e-mode GaN transistors, compared to their silicon MOSFET predecessors. Accordingly, when e-mode GaN transistors, particularly non-ground referenced e-mode GaN transistors, are driven, gate drive circuits must be designed so as to avoid the exceeding maximum gate drive voltage of the transistor.
For many power electronics topologies, a non-ground referenced power transistor is used, including the half bridge based topologies such as synchronous buck, synchronous boost, isolated full bridge, isolated half bridge, LLC, and many others. The gate voltage for the non-ground referenced device is generated using a bootstrap circuit—the circuit, current flow, and timing diagram for a buck converter configuration are shown in FIGS. 1A, 1B-1D, and 1E, respectively.
As shown in FIG. 1A, the conventional buck converter bootstrap driver circuit includes a pair of transistors 12 and 14 labeled Q1 and Q2. Typically, the transistors 12 and 14 are referred to as high side and low side switches, respectively. The source of high side transistor 12 is coupled to the drain of low side transistor 14 at the half bridge output (VSW). The drain of high side transistor 12 is coupled to a high voltage source 18 (VIN), and the source of low side transistor 14 is coupled to ground. Furthermore, the gate of high side transistor 12 is coupled to the gate drive output GH of a gate driver IC, and the gate of low side transistor 14 is coupled to the gate drive output GL of the gate driver IC. Gate drivers are well-known in the art and will not be described in detail herein. However, it should be understood that this configuration enables one transistor 12 or 14 (Q1 or Q2) to be switched on and the other transistor to be switched off and vice versa during operation.
As further shown in FIG. 1A, a driving voltage source 20 (VDR) is coupled to an input of the gate driver IC. A bootstrap capacitor 22 (CB) is coupled in parallel with the gate driver IC and a bootstrap diode 24 (DB) is coupled between the driving voltage source 20 (VDR) and the bootstrap capacitor 22 (CB).
During the periods t1 and t2 (FIG. 1E), when the ground referenced (low side) transistor 14 (Q2) is conducting (indicated in FIGS. 1B and 1C by the current path from driving voltage source 20 (VDR) to ground, through transistor 14 (Q2)), the floating bootstrap capacitor 22 (CB) is effectively grounded and the bootstrap capacitor can be charged. Specifically, when the low side transistor 14 (Q2) is conducting, the bootstrap capacitor 22 (CB) is charged to:VCB=VDR−VRDB−VDB+VQ2 where VDR is the driver voltage, VDB is the forward drop of the bootstrap diode 24, VRDB is the voltage drop across an optional resistor RDB to limit bootstrap capacitor charging speed, and VQ2 is the voltage across the low side transistor 14 (Q2). When the bootstrap capacitor 22 (CB) is fully charged, the bootstrap diode 24 (DB) will begin to block and end the charging cycle.
During the on-cycle of high side transistor 12 (Q1), the bootstrap capacitor 22 (CB), referenced to the driver IC gate return (GR), which is equivalent to the switch node (VSW), is used to drive the high side device 12 (Q1) through driver IC gate output (GH). The bootstrap driving period is identified by t3 in FIG. 1E, and the current path is shown in FIG. 1D.
When the low side device 14 (Q2) is driven on, time interval t1, there will be a voltage drop (V≈0.3˜0.7 V) across the bootstrap diode 24 (DB), and a small voltage generated by the load across Q2, (ILOAD RDS(ON)), and the bootstrap capacitor voltage VCB, defined in the equation above, will remain below the set driver voltage, VDR, and VCB≈4.0˜4.7 V, with the capacitor voltage depending on diode and device characteristics and the operating conditions of the circuit (e.g., ILOAD). As shown in FIG. 1E, this period, t1, is generally a large portion of the overall period, TSW=1/fSW, and the range well defined, and therefore is the intended charging period for the bootstrap capacitor. In the majority of applications, designers seek to minimize the charging times required for the bootstrap capacitor 22 (CB), and no optional charge limiting resistor, RDB, is used for standard designs. The bootstrap diode 24 (DB) generally has a large enough equivalent resistive drop to ensure proper charging currents.
During the dead-time, time interval t2, when Q1 and Q2 are both driven off, the “body-diode” function of the e-mode GaN transistor conducts the load current. GaN transistors do not have a p-n junction body diode as is common in silicon MOSFETs. With zero gate-to-source voltage, the GaN transistor has no electrons under the gate region and is off. As the drain voltage decreases, a positive bias on the gate is created, and, when the threshold voltage is reached, there are sufficient electrons under the gate to form a conductive channel. The GaN transistor's majority carrier “body-diode” function has the benefit of no reverse recovery charge, QRR, which is very beneficial in high frequency switching, but produces a larger forward drop than a conventional silicon MOSFET body diode. The larger forward drop will increase the related conduction losses and create an overvoltage condition for an e-mode GaN transistor in a conventional bootstrap drive circuit.
More specifically, during the dead-time, time interval t2, the larger reverse conduction voltage (typically 2-2.5 V) of the low side GaN transistor 14 (Q2), compared to the voltage drop (0.3-0.7 V) of the bootstrap diode 24 (DB), will increase the voltage across the bootstrap capacitor 22 (CB), following the above equation, resulting in the potential overcharging of the bootstrap capacitor 22 (CB) above VDR, potentially damaging and limiting the lifetime of the high side transistor 12 (Q1) when it is driven.
The gate-to-source waveforms of a GaN based design with the conventional bootstrapping circuit of FIG. 1A are shown in FIG. 2. For both t2 dead-time conditions (t2≈0 ns and t2≈6 ns), the lower gate voltage, VGS(Q2), remains constant around a VDR driver supply voltage set-point and the waveforms overlap very closely. For the maximum dead-time, the bootstrap capacitor voltage and upper gate, VGS(Q1), is measured to be approximately 6 VDC (t2≈6 ns), well above desired operating range, and the gate reaches an almost 7 V peak in the voltage spike, well above the 6 V maximum peak gate voltage of GaN transistors. For the no load case, where period t2 is eliminated (t2≈0 ns), the bootstrap capacitor voltage is measured to be approximately 4.4 VDC, near the intended voltage. Thus, FIG. 2 demonstrates the issue of bootstrap capacitor overcharging during the t2 dead-time period when using a conventional bootstrapping drive method for e-mode GaN transistors.
A number of modified bootstrap drive circuits which avoid the bootstrap capacitor overvoltage condition described above have been proposed in the prior art.
In U.S. Pat. No. 8,593,211, an active clamping switch is inserted in series with the bootstrap diode. During the dead-time t2, the clamping switch is driven off to disconnect the charging path, limiting over-voltage. This design advantageously actively controls bootstrap charging periods. However, such a design adds complexity—an IC must actively monitor and compare various circuit operating conditions, and the additional device (the active clamping switch) introduces higher IC parasitic losses.
Another prior art solution to the above-described over-voltage issue is to insert a Zener diode parallel to the bootstrap capacitor. The Zener diode clamps the voltage across the bootstrap capacitor (CB) when the bootstrap capacitor voltage exceeds the Zener voltage of the diode. Such a solution is simple, requiring the addition of only a single component (a Zener diode) to the circuit. However, clamping is a dissipative method where the over-voltage is dissipated in the Zener. Thus, this circuit has the highest gate drive loss of all prior art solutions.
Another prior art solution to the over-voltage issue is to insert a Schottky diode in parallel with the low side e-mode GaN transistor (Q2). During the dead-time t2, the Schottky diode, which has a much lower forward voltage than the e-mode GaN device (Q2), will conduct, limiting over-voltage. Although adding a Schottky diode in parallel with Q2 limits over-voltage and minimizes power stage losses, the effectiveness of this solution is highly dependent on performance and package parasitics of the Schottky diode. For many applications, e.g. higher voltages and higher currents, there is no suitable Schottky diode and the circuit is not implementable.
Yet another prior art solution is to add not only a Schottky diode, as in the above solution, to provide a low voltage drop path to charge the bootstrap capacitor, but also add a gate resistor to limit the power current that can flow though the Schottky diode, thereby improving the selection of available Schottky diodes. The gate resistor acts as a turn on and turn off resistor for the high side transistor Q1. However, increasing the turn on and turn off resistance significantly increases switching related losses in the Q1 power device and significantly degrades power stage performance. Moreover, especially for high voltage applications, there is no suitable DQ2 and the solution is thus limited or not implementable.
Another prior art circuit is a synchronous bootstrap GaN FET, described in U.S. Pat. No. 9,667,245. This circuit, in which the bootstrap diode is replaced with an e-mode GaN transistor that is driven from the gate of Q2, actively regulates over-voltage and minimizes high frequency drive losses. The disadvantage is in the complexity of this circuit. Additional components are required. Moreover, the bootstrap transistor must be a high voltage transistor that can block the full half bridge supply voltage.
Accordingly, a need exists for a drive circuit which avoids the bootstrap capacitor overvoltage condition described above, and also overcomes the deficiencies of the prior solutions described above.